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1 isl8012 2a low quiescent current 1mhz high efficiency synchronous buck regulator isl8012 the isl8012 is a high efficiency, monolithic, synchronous step-down dc/dc converter that can deliver up to 2a continuous output current from a 2.7v to 5.5v input supply. it uses a current control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the isl8012 integrates a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. the 100% duty-cycle operation allows less than 240mv dropout voltage at 2a output current. high 1mhz pulse width modulation (pwm) switching frequency allows the use of small external components. the isl8012 can be configured for discontinuous or forced continuous operation at light load. forced continuous operation reduces noise and rf interference while discontinuous mode provides high efficiency by reducing switching losses at light loads. fault protection is provided by internal current limiting during short circuit and overcurrent conditions, an output overvoltage comparator and over-temperature monitor circuit. a power-good output voltage monitor indicates when the output is in regulation. the isl8012 offers a 1ms power-good (pg) timer at power-up. when shutdown, isl8012 discharges the output capacitor. other features include internal soft-start, internal compensation, overcurrent protection, and thermal shutdown. the isl8012 is offered in a space saving 3mmx3mm 10 ld dfn package lead free package with exposed pad lead frames for low thermal. the complete converter occupies less than 0.35in 2 area. features ? high efficiency synchronous buck regulator with up to 95% efficiency ? power-good (pg) output with a 1ms delay ? 2.7v to 5.5v supply voltage ? 3% output accuracy over-temperature/load/line ? 2a guaranteed output current ? start-up with pre-biased output ? internal soft-start - 1ms ? soft-stop output discharge during disabled ? 40a quiescent supply current in pfm mode ? selectable forced pwm mode and pfm mode ? less than 1a logic controlled shutdown current ? 100% maximum duty cycle ? internal current mode compensation ? peak current limiting and hiccup mode short circuit protection ? over-temperature protection ? small 10 ld 3mmx3mm dfn ? pb-free (rohs compliant) applications* (see page 15) ? dc/dc pol modules ?c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ?portable instruments ? test and measurement systems ? li-ion battery powered devices ? small form factor (sfp) modules ? bar code readers related literature* (see page 15) ?see an1360 for ?isl8012eval1z: 2a synchronous buck regulator with integrated mosfets? caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. fn6616.1 march 17, 2010
2 march 17, 2010 fn6616.1 pin configuration isl8012 (10 ld dfn) top view vin vcc en pg lx pgnd sgnd vfb mode rsi 2 3 4 1 5 9 8 7 10 6 pd pin descriptions symbol pin number description vin 1 input supply voltage. connect a 10 f ceramic capacitor to power ground. vcc 2 input supply for the logic. connect to vin. en 3 regulator enable pin. enable the output when driven to high. shutdown the chip and discharge output capacitor when driven to lo w. do not leave this pin floating. pg 4 1ms timer output. at power-up or en hi, this output is a 1ms delayed power-good signal for the output voltage. this output can be reset by a lo w rsi signal. 1ms starts when rsi goes to high. mode 5 mode selection pin. connect to logic high or input voltage vin for pfm mode; connect to logic low or ground for forced pwm mode. do not leave this pin floating. rsi 6 this input resets the 1ms timer. when the output voltage is within the pgood window, an internal timer is started and generates a pg signal 1ms late r when rsi is low. a high rsi resets pg and rsi high to low transition restarts the internal count er if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. vfb 7 buck regulator output feedback . connect to the output through a resistor divider for adjustable output voltage (isl8012-adj). for preset output voltage, connect this pin to the output. sgnd 8 system ground for the control logic. all voltag e levels are measured with respect to this pin. pgnd 9 ground connect for the ic and thermal relief fo r the package. the expose d pad must be connected to pgnd and soldered to the pcb. lx 10 switching node connection. conn ect to one terminal of inductor. exposed pad pd the exposed pad must be connected to the pgnd and sgnd pin for prop er electrical performance. the exposed pad must also be connected to as mu ch as possible for optimal thermal performance. isl8012
3 march 17, 2010 fn6616.1 typical application block diagram figure 1. typical application diagram l lx pgnd vfb rsi vin en pg mode input 2.7v to 5.5v output 1.8v/2a c1 2x10f r1 100k isl8012 c2 r2 124k r3 100k 2x10f sgnd c3* 220pf *c3 is optional figure 2. functional block diagram lx + + csa + + ocp 1v 0.25v skip + + + slope comp soft-start 0.8v eamp comp pwm/pfm logic controller protection driver vfb + 0.736v 0.864v pg mode shutdown vin gnd oscillator zero-cross sensing + bandgap scp + 0.2v en shutdown 1ms delay rsi 27pf 390k isl8012
4 march 17, 2010 fn6616.1 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl8012irz 012z -40 to +85 10 ld 3x3 dfn l10.3x3c notes: 1. add ?-t? or suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl8012 . for more information on msl please see techbrief tb363 . isl8012
5 march 17, 2010 fn6616.1 absolute maximum ratings (reference to gnd) thermal information vin, vcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v en, rsi, pg . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin+0.3v lx . . . . . . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6.5v vfb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v recommended operating conditions v in supply voltage range . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . 0a to 2a ambient temperature range . . . . . . . . . . . . -40c to +85c esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . 5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . 300v thermal resistance (typical) ja (c/w) jc (c/w) 10 ld 3x3 dfn (notes 4, 5) . . . . 49 5.5 junction temperature range . . . . . . . . . . -55c to +125c storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specifications are measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en = vcc, unless otherwis e noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 7) typ max (note 7) units input supply vin undervoltage lockout threshold v uvlo rising 2.5 2.7 v falling 2.2 2.4 v quiescent supply current i vin mode = vin, no load at the output 40 60 a mode = vin, no load at the output and no switches switching; design info only 15 a mode = sgnd, no load at the output 6 8 ma shut down supply current i sd v in = 5.5v, en = low 0.1 2 a output regulation vfb regulation voltage v vfb t a = 0c to +85c 0.784 0.8 0.816 v vfb bias current i vfb vfb = 0.75v 0.1 a output voltage accuracy v in = v o + 0.5v to 5.5v, i o = 0a to 2a (note 6) -3 3 % line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v), i out = 400ma 0.2 %/v compensation error amplifier trans-conductance adjusta ble version, design info only 20 a/v lx p-channel mosfet on-resistance v in = 5.5v, i o = 200ma 0.12 0.22 v in = 2.7v, i o = 200ma 0.21 0.27 n-channel mosfet on-resistance v in = 5.5v, i o = 200ma 0.11 0.22 v in = 2.7v, i o = 200ma 0.13 0.27 p-channel mosfet peak current limit i pk 2.65 3.00 3.50 a lx maximum duty cycle 100 % isl8012
6 march 17, 2010 fn6616.1 pwm switching frequency f s t a = 0c to +85c 0.840 1 1.16 mhz lx minimum on-time mode = low (forced pwm mode) 80 100 ns soft-start-up time v in = 3.6v 1.1 ms pg output low voltage sinking 1ma, vfb = 0.7v 0.3 v delay time 1ms pg pin leakage current pg = v in = 3.6v 0.01 0.1 a minimum supply voltage for valid pg signal 1.2 v internal pgood low risi ng threshold percentage of nominal regulation voltage 89 92 95 % internal pgood low falling threshol d percentage of nominal regulation voltage 85 88 91 % internal pgood high risi ng threshold percentage of nominal regulation voltage 107 110 113 % internal pgood high falling threshol d percentage of nominal regulation voltage 104 107 110 % internal pgood delay time 30 s en, mode, rsi logic input low 0.4 v logic input high 1.4 v logic input leakage current pulled up to 5.5v 0.1 1 a notes: 6. limits established by characterization and are not production tested. 7. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and ar e not production tested. electrical specifications unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specifications are measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en = vcc, unless otherwis e noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 7) typ max (note 7) units isl8012
7 march 17, 2010 fn6616.1 isl8012 typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , mode = 0v, l = 2.2h, c 1 = 2x10f, c 2 = 2x10f, i out = 0a to 2a) . figure 3. efficiency vs load (1mhz 3.3v in pwm) figure 4. efficiency vs load (1mhz 3.3v in pfm) figure 5. efficiency vs load ( 1mhz 5v in pwm) figure 6. efficiency vs load ( 1mhz 5v in pfm ) figure 7. power dissipation vs load (1mhz, v out = 1.8v) figure 8. power dissipation with no load vs v in (pwm v out = 1.8v) 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) efficiency (%) 2.5v out 1.2v out 1.8v out 1.5v out 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) 20 30 40 50 60 70 2.5v out 1.2v out 1.8v out 1.5v out efficiency (%) 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) efficiency (%) 20 30 40 50 60 70 80 90 100 2.5v out 1.8v out 1.5v out 1.2v out 3.3v out 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) efficiency (%) 20 30 40 50 60 70 80 90 100 2.5v out 1.8v out 1.5v out 1.2v out 3.3v out 0 0.125 0.250 0.375 0.500 0.625 0.750 0.875 1.000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) power dissipation (w) 5v in pfm 3.3v in pfm 5v in pwm 3.3v in pwm 0 0.125 0.250 0.375 0.500 0.625 0.750 0.875 1.000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) power dissipation (w) 5v in pfm 3.3v in pfm 5v in pwm 3.3v in pwm 0 20 40 60 80 100 120 140 160 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v in (v) power dissipation (mw) pwm mode
8 march 17, 2010 fn6616.1 figure 9. power dissipation with no load vs v in (pfm v out = 1.8v) figure 10. v out regulation vs load (1mhz, v out = 1.2v) figure 11. v out regulation vs load (1mhz, v out = 1.5v) figure 12. v out regulation vs load (1mhz, v out = 1.8v) figure 13. v out regulation vs load (1mhz, v out = 2.5v) figure 14. v out regulation vs load (1mhz, v out = 3.3v) typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , mode = 0v, l = 2.2h, c 1 = 2x10f, c 2 = 2x10f, i out = 0a to 2a) . (continued) 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v in (v) power dissipation (mw) pfm 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) output voltage (v) 5v in pfm 3.3v in pfm 5v in pwm 3.3v in pwm 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) output voltage (v) 5v in pfm 3.3v in pfm 5v in pwm 3.3v in pwm 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) output voltage (v) 3.3v in pfm 5v in pwm 3.3v in pwm 5v in pfm 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) 3.3v in pfm 3.3v in pwm 5v in pwm 5v in pfm 2.43 2.45 2.47 2.49 2.51 2.53 2.55 2.57 2.59 output voltage (v) 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 output voltage (v) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 output load (a) 5v in pwm 4.5v in pwm 4.5v in pfm 5v in pfm isl8012
9 march 17, 2010 fn6616.1 figure 15. steady state operation at no load (pwm), (1s/div) figure 16. steady state operation at no load (pfm), (1s/div) figure 17. steady state operation with full load, (5s/div) figure 18. mode transition ccm to dcm, (5s/div) figure 19. mode transition dcm to ccm, (50s/div) figure 20. load transient (pwm), (50s/div) typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , mode = 0v, l = 2.2h, c 1 = 2x10f, c 2 = 2x10f, i out = 0a to 2a) . (continued) vout ripple 20mv/div il 0.5a/div lx 2v/div vout ripple 20mv/div lx 2v/div il 0.5a/div vout ripple 20mv/div il 0.5a/div lx 2v/div vout ripple 50mv/div il 0.5a/div lx 2v/div vout ripple 50mv/div il 0.5a/div lx 2v/div vout ripple 50mv/div il 1a/div isl8012
10 march 17, 2010 fn6616.1 figure 21. load transient (pfm), (500s/div) f igure 22. soft-start with no load (pwm), (500s/div) figure 23. soft-start at no load (pfm), (500s/div) figure 24. soft-start with pre-biased 1v, (500s/div) figure 25. soft-start at full load, (2ms/div) figure 26. soft-discharge shutdown, (2ms/div) typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , mode = 0v, l = 2.2h, c 1 = 2x10f, c 2 = 2x10f, i out = 0a to 2a) . (continued) vout ripple 50mv/div il 1a/div lx 2v/div vout 0.5v/div il 0.5a/div en 5v/div pg 5v/div vout 0.5v/div en 2v/div pg 5v/div il 0.5a/div vout 0.5v/div il 0.5a/div en 2v/div pg 5v/div vout 0.5v/div il 1a/div en 2v/div pg 5v/div vout 0.5v/div il 1a/div en 5v/div pg 5v/div isl8012
11 march 17, 2010 fn6616.1 figure 27. rsi reset, (200s/div) figure 28. rsi reset (zoom out), (200s/div) figure 29. output short circuit, (500s/div ) figure 30. output short circuit recovery, (500s/div) figure 31. output current limit vs temperature typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 2.5v to 5.5v, en = v in , mode = 0v, l = 2.2h, c 1 = 2x10f, c 2 = 2x10f, i out = 0a to 2a) . (continued) vout ripple 20mv/div rsi 2v/div pg 2v/div vout ripple 20mv/div pg 2v/div rsi 2v/div vout 0.5v/div il 2a/div phase 2v/div pg 5v/div vout 1v/div il 2a/div lx 2v/div pg 5v/div 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 -50-250255075100 temperature (c) output current limit (a) 3.3v in 5.5v in isl8012
12 march 17, 2010 fn6616.1 theory of operation the isl8012 is a step-down switching regulator optimized for battery-powered handheld applications. the regulator operates at 1mhz fixed switching frequency under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator reduces the switching frequency (unless forced to the fixed frequency) to minimize the switching loss and to maximize the battery life. the quiescent current when the output is not loaded is typically only 40a. the supply current is typically only 0.1a when the regulator is shut down. pwm control scheme pulling the mode pin low (<0.4v) forces the converter into pwm mode, regardless of output current. the isl8012 employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting. figure 2 shows the block diagram. the current loop consists of the oscillator, the pwm comparator, current sensing circuit and the slope compensation for the current loop stability. the gain for the current sensing circuit is typically 285mv/a. the control reference for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp-up. when the sum of the current amplifier csa and the slope compensation (675mv/s) reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 32 shows the typical operating waveforms during the pwm operation. the dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier?s csa output. the output voltage is regulated by controlling the v eamp voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 390k rc network. the maximum eamp voltage output is precisely clamped to 1.47v. skip mode pulling the mode pin high (>1.4v) forces the converter into pfm mode. the isl8012 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 33 illustrates the skip-mode operation. a zero-cross sensing circuit shown in figure 2 monitors the n-mosfet current for zero crossing. when 8 consecut ive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. during the 8 detecting cycles, the current in the inductor is allowe d to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in figure 2. each pulse cycle is still synchronized by the pwm clock. the p-mosfet is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak skip current limit value. then the inductor current is discharging to zero ampere and stays at zero. the internal clock is disabled. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-mosfet will be turned on again at the rising edge of the internal clock as it repeats the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. figure 32. pwm operation waveforms v eamp v csa duty cycle i l v out figure 33. skip mode operation waveforms clock i l v out skip current limit load current 0 8 cycles nominal +1.5% nominal isl8012
13 march 17, 2010 fn6616.1 mode control the isl8012 has a mode pin that controls the operation mode. when the mode pin is driven to low or shorted to ground, the regulator operates in a forced pwm mode. the forced pwm mode remains the fixed pwm frequency at light load instead of entering the skip mode. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in figure 2. the current sensing circuit has a gain of 285mv/a, from the p-mosf et current to the csa output. when the csa output reaches 1v, which is equivalent to 2.9a for the switch current (0.15v offset), the ocp comparator is trippe d to turn off the p-mosfet immediately. the overcurren t function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. short-circuit protection the short-circuit protection scp comparator monitors the vfb pin voltage for output short-circuit protection. when the vfb is lower than 0.2v, the scp comparator forces the pwm oscillator frequency to drop to minimum value to reduce the power dissipation. this comparator is effective during start-up or an output short-circuit event. rsi/pg function when powering up, the open-collector power-good output holds low for about 1ms after v o reaches the preset voltage. when the active-hi reset signal rsi is issued, pg goes to low immediately and holds for the same period of time after rsi comes back to low. the output voltage is unaffected. please refer to the timing diagram in figure 34. when the function is not used, connect rsi to ground and leave the pull-up resistor r 4 open at the pg pin. the pg output also serves as a 1ms delayed power-good signal when the pull-up resistor r 1 is installed. the rsi pin needs to be directly (or indirectly through a resistor) connected to ground for pg to be actively monitoring the output voltage. uvlo when the input voltage is below the undervoltage lock-out (uvlo) threshold, the regulator is disabled. soft start-up the soft-start-up reduces the in-rush current during the start-up. the soft-start block outputs a ramp reference to the input of the error amplifie r. this voltage ramp limits the inductor current as well as the output voltage speed so that the output voltage rises in a controlled fashion. when vfb is less than 0.2v at the beginning of the soft- start, the switching frequency is reduced to 1/3 of the nominal value so that the output can start up smoothly at light load condition. during soft-start, the ic operates in the skip mode to support pre-biased output condition. enable the enable (en) input allows the user to control the turning on or off the regulator for purposes such as power-up sequencing. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft-start-up begins. discharge mode (soft-stop) when a transition to shutdown mode occurs or the vin uvlo is set, the outputs discharge to gnd through an internal 100 switch. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-mosfet is typically 120m and the on-resistance for the n-mosfet is typically 110m . 100% duty cycle the isl8012 features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the isl8012 can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shut-down the isl8012 has built-in thermal protection. when the internal temperature reaches +140c, the regulator is completely shut down. as the temperature drops to +115c, the isl8012 resumes operation by stepping through the soft-start. applications information output inductor and capacitor selection to consider steady state and transient operations, isl8012 typically uses a 2.2h output inductor. the higher or lower inductor value can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. it is recommended to set the ripple inductor current min 25ns 1ms pg rsi v o figure 34. rsi and pg timing diagram 1ms isl8012
14 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com march 17, 2010 fn6616.1 for additional products, see www.intersil.com/product_tree approximately 30% of the maximum output current for optimized performance. the in ductor ripple current can be expressed as shown in equation 1: the inductor?s saturation current rating needs to be at least larger than the peak current. the isl8012 protects the typical peak current 6a. the saturation current needs be over 7a for maximum output current application. isl8012 uses an internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended x5r or x7r minimum output capacitor values are shown in table 1. in table 1, the minimum output capacitor value is given for the different output voltage to make sure that the whole converter system is stable. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to figure 1. the output voltage programming resistor, r 3 , will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor is typically between 10k and 100k , as shown in equation 2. if the output voltage desired is 0.8v, then r 3 is left unpopulated and r 2 is shorted. for better performance, add 220pf in parallel with r 2 (124k ). input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current from flowing back to the battery rail. two 10f x5r or x7r ceramic capacitors are a good starting point for the input capacitor selection. layout recommendation the layout is a very important converter design step to make sure the designed converter works well. for the isl8012 buck converter, the power loop is composed of the output inductor l, the output capacitor c out , lx pin and sgnd pin. it is necessary to make the power loop as small as possible. the heat of the ic is ma inly dissipated through the thermal pad. maximizing the copper area connected to the thermal epad is preferable. in addition, a solid ground plane on the second layer is helpful for emi performance. then connect the epad to the ground plane with at lease 5 vias for best thermal performance. table 1. output capacitor value vs v out v out (v) c out (f) l (h) 0.8 2x10 1.5~3.3 1.2 2x10 1.5~3.3 1.5 2x10 1.8~3.3 1.8 2x10 2.2~3.3 2.5 2x10 2.2~4.7 3.3 2x10 2.2~4.7 3.6 2x10 2.2~4.7 i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) r 3 r 2 0.8v v out 0.8v ? ---------------------------------- = (eq. 2) isl8012
15 march 17, 2010 fn6616.1 products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl8012 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only an d is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 2010-03-17 fn6616.1 added ?related literature? to page 1 per new data sheet standards. moved ?pin configuration? to page 2 and converted ?pin descriptions? on page 2 to tabular format, per new data sheet standards. added inverter symbol on the rsi pi n in the ?block diagram? on page 3. added esd ratings to ?absolute maximum ratings (r eference to gnd)? on page 5 per new data sheet standards. added ?revision history? on page 15 and ?produ cts? on page 15 per new data sheet standards. 2009-10-29 on page 2: redrew chamfered corner on pinout to look like pod on page 15 on page 7 to page 11 in common conditions of ?t ypical performance curves ?: changed "l = 1.5h to 2.2h" to "l = 2.2h? ?input capacitor selection? on page 14: changed "two 22f x5r or x7r ceramic capacitors are a good starting point.." to "two 10f x5r or x7r ceramic capacitors are a good starting point.." 2009-10-27 on page 16: updated pod to latest revision (changes from rev 0 to rev 1 were to add land pattern and move dimensions from table onto drawing) ?typical application? on page 3: changed value of c1 & c2 from 22f to 2x10f. n page 7 to page 11 in common conditions of ?typic al performance curves?: changed "l = 1.5h" to "l = 1.5h to 2.2uh" on page 14 in table 1: ch anged value of all cout caps from 22f to 2x10f. ?input capacitor selection? on page 14: changed "o ne 22f x5r or x7r ceramic capacitor is a good starting point.." to "two 22f x5r or x7r ce ramic capacitors are a good starting point.." throughout: converted to new format. a dded new required content as follows: on page 4: added msl note 3 to ?ordering information? on page 5: in the ?electrical specifications?: adding standard over temp note to common conditions ("boldface limits apply...) moved note 7 "parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature li mits established by char acterization and are not production tested" from common conditions to min max columns as part of new standard ?thermal information? on page 5: updated thet a jc note 5 from "thetajc, ?case temperature? location is at the center of the exposed metal pa d on the package underside. see tech brief tb379." to "for thetajc, the ?case temp? location is the center of the exposed metal pad on the package underside." per asyd re cord and new standards 2009-07-15 on page 2 in pinout: deleted the circle and ch amfered the corner of thermal pad (to match pod). re- drew pins 1, 5, 6, 10 to l ook the same as the other pins updated pb-free note 2 in ?ordering information? on page 4 based on lead finish, per packaging. on page 5: in the ?electrical specifications?: re moved note "parts are 1 00% tested at +25c. temperature limits established by characterization and are not production tested." from min max columns and replaced with new ve rbiage in common conditions "p arameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested." 2008-03-11 fn6616.0 initial release. isl8012
16 march 17, 2010 fn6616.1 isl8012 package outline drawing l10.3x3c 10 lead dual flat package (dfn) rev 2, 09/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.10 c 2 6 10 1 package 0.90 0.20 0.50 2.38 3.00 (10x 0.25) (8x 0.50) 2.38 1.64 (10 x 0.60) 3.00 0.05 0.20 ref 10 x 0.25 10x 0.40 1.64 outline cb max (4x) 0.10 cb 5 m 7. complaint to jedec mo-229-weed-3 except for e-pad dimensions.

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